1. Field of the Invention
The present invention relates to a circuit substrate. More particularly, the present invention relates to a chip carrier and a chip package structure thereof.
2. Description of the Related Art
With the rapid progress in electronic technologies, high-tech products having more functions and humanized setup are introduced everyday. Furthermore, a light and compact body is the design trend in most electronic products. In the fabrication of semiconductors, chip carrier is one of the most common structural components. A chip carrier can be an organic dielectric substrate or an inorganic dielectric substrate comprising a plurality of alternately laid patterned conductive layers and dielectric layers. The dielectric layer is disposed between two adjacent patterned conductive layers and the patterned conductive layers can be electrically connected through a plating through hole (PTH) or a via passing through the dielectric layers. Since a chip carrier can provide a dense wiring, compact assembly and good electrical performance, it has become one of the preferred elements for fabricating chip packages.
According to the process of attaching and electrically connecting a chip to a chip carrier, chip packages are classified into wire-bonding package and flip-chip bonding packages. FIG. 1 is a schematic cross-sectional view showing part of a conventional wire-bonding chip package structure. The chip package structure 100 in FIG. 1 essentially comprises a chip 110, a plurality of bonding wires 116 and a chip carrier 120. Bonding pads 114 on the chip 110 are electrically connected to the bonding finger pads 124 on the surface 122 of the chip carrier 120 through bonding wires 116. Since the bonding wires 116 are broadly fabricated by gold, the cost of fabricating wire-bonding packages is high. Besides, in order to prevent the oxidation, a nickel/gold (Ni/Au) layer 128 serving as an anti-oxidation layer is formed over the surface of the bonding finger pads 124 outside the solder mask layer 140 or the surface of the lower contacts 126 for connecting with external devices. The nickel/gold layer 128 also serves as an adhesion layer for enhancing the bonding strength between a solder ball 160 and corresponding lower contact 126.
It should be noted that the conventional electroplating method of forming a nickel/gold layer has the following disadvantages:
1. The time and cost involved in performing an electroplating operation is too high. Therefore, plating a nickel/gold film over the bonding finger pad to serve as an oxidation protection layer increases the production cost of the package.
2. At least one plating line connecting all the bonding finger pads has to be fabricated on the chip carrier before the electroplating process. However, the plating line will occupy some layout area on the chip carrier and reduce the effective area for forming other circuits or devices.
3. The plating line may affect the electrical performance of the chip package.
4. Nickel has a relatively high resistance and may contain some impurities. Ultimately, the signal transmission quality may be affected.
In view of the foregoing, if the process of electroplating a nickel/gold film can somehow be unnecessary, the time and cost to fabricate a chip carrier can be reduced and the effective area of the chip carrier can be increased. Moreover, the electrical performance of the chip package is improved. That is why the present invention concerned to overcome.